1. Field of the Invention
The present invention relates to interconnection structures, and, more particularly, to an interconnection structure for a semiconductor package.
2. Description of Related Art
To meet the trend of multi-function and high electrical performance of electronic products, various types of structures have been developed for semiconductor packages. For example, a semiconductor element is disposed on and electrically connected to a packaging substrate through a plurality of solder bumps and then encapsulated to form a semiconductor package. The semiconductor element has a plurality of bonding pads, and the packaging substrate has a plurality of conductive pads. The bonding pads of the semiconductor element are aligned with and electrically connected to the conductive pads of the packaging substrate through the solder bumps.
Referring to FIG. 1, a substrate 30 such as a semiconductor chip having a plurality of bonding pads 300 made of aluminum (only one bonding pad 300 is shown) is provided. An insulating layer 301 is formed on the substrate 30, and a plurality of openings are formed in the insulating layer 301 for exposing the bonding pads 300. A titanium layer 11, a copper layer 12, and a nickel layer 13 are sequentially formed on the bonding pads 300 to serve as an under bump metallurgy (UBM) layer, and then a solder material 15 is formed on the nickel layer 13. As such, the titanium layer 11, the copper layer 12, the nickel layer 13, and the solder material 15 form an interconnection structure 1. The solder material 15 is reflowed to form solder bumps. During the reflow process, an intermetallic compound 13′ is formed at interfaces between the nickel layer 13 and the solder bumps.
Conventionally, the intermetallic compound 13′ is a nickel-tin compound (NixSny) such as Ni3Sn4. The intermetallic compound 13′ is brittle, and easily impairs the mechanical strength, the lifetime and the fatigue strength of the solder bumps. Therefore, bump cracking or delamination is likely found in a reliability test at the interfaces between the UBM layer and the solder bumps, thereby reducing the product yield.
Therefore, how to overcome the above-described drawbacks has become critical.